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RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE
Data Sheet July 1999 File Number 2407.4
12A, 60V, 0.135 Ohm, N-Channel, Logic Level, Power MOSFETs
[ /Title (RFD1 2N06R LE, RFD12 N06RL ESM, RFP12 N06RL E) /Subject 12A, 0V, .135 hm, hanel, ogic evel, ower OSETs) /Autho () /Keyords Interil orpoation, hanel, ogic evel, ower OSThese N-Channel logic level ESD protected power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor drivers, relay drivers, and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09861.
Features
* 12A, 60V * rDS(ON) = 0.135 * Electrostatic Discharge Protected * UIS Rating Curve (Single Pulse) * Design Optimized for 5V Gate Drive * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER RFD12N06RLE RFD12N06RLESM RFP12N06RLE PACKAGE TO-251AA TO-252AA TO-220AB BRAND 12N6LE 12N6LE 12N06RLE
G
S
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e., RFD12N06RLESM9A.
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE
JEDEC TO-252AA
DRAIN (FLANGE) GATE SOURCE
DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE 60 60 12 26 -5 to10 40 0.32 Refer to UIS SOA Curve 2 -55 to 150 300 260
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Electrostatic Discharge Rating ESD, MIL-STD-883, Category B(2) Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
UNITS V V A A V W W/oC kV
oC oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC MIN 60 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 48V, ID = 12A, RL = 4, IG(REF) = 0.25mA (Figures 17, 18) TO-251AA and TO-252AA TO-220AB TYP 12 20 24 12 MAX 2 1 25 10 0.135 0.160 60 60 40 20 1.5 3.125 100 62 UNITS V V A A A ns ns ns ns ns ns nC nC nC
oC/W oC/W oC/W
Gate to Source Leakage Current Drain to Source On Resistance (Note 2)
IGSS rDS(ON)
VGS = -5 to 10V ID = 12A, VGS = 5V (Figures 7, 8) ID = 12A, VGS = 4V VDD = 30V, ID 6A, RL = 5, RGS = 6.25, VGS = 5V, (Figures 15, 16)
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(5) Qg(TH) RJC RJA
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time NOTES: 2. Pulse test: pulse width 300ms, duty cycle 2%. 3. Repetitive rating: pulse width is limited by maximum junction temperature. SYMBOL VSD trr ISD = 12A ISD = 12A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.2 200 UNITS V ns
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RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A) 10
Unless Otherwise Specified
15
0.6 0.4
5
0.2 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
100 TJ = MAX RATED TC = 25oC ID, DRAIN CURRENT, (A) ID MAX CONTINUOUS 10 DC OPERATION OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
100 IAS, AVALANCHE CURRENT (A) If R = 0 tav = (L)(Ias) / (1.3 RATED BVDSS - VDD) If R 0 tav = (L/R) In ((Ias x R) / (1.3 RATED BVDSS - VDD) + 1)
Idm
10
STARTING TJ = 25oC STARTING TJ = 150oC
1
0.1
1
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
100
1 0.01
0.1 1 tAV, TIME IN AVALANCHE (ms)
10
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
IDS(ON), DRAIN TO SOURCE CURRENT (A) 30
30 VGS = 10V ID, DRAIN CURRENT (A) VGS = 5V VGS = 4V 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 10 VGS = 3V
PULSE DURATION = 80s DUTY CYCLE = 0.5 % MAX VDS = 15V -55oC
25oC 150oC
20
10
VGS = 2V 0 0 1.5 3 4.5 6 VDS, DRAIN TO SOURCE VOLTAGE (V) 7.5
0
0
1.5 3 4.5 6 VGS, GATE TO SOURCE VOLTAGE (V)
7.5
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
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RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Typical Performance Curves
1.4 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDS = 15V, ID = 12A 1.3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.2 1.1 1.0 0.9 0.8 0.7 0.6 4.0 4.5 5.0 5.5 6.0 6.5 VGS, GATE TO SOURCE VOLTAGE (V) 7.0
Unless Otherwise Specified (Continued)
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
2.0
ID = 12A, VGS = 5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5
1.0
0.5
0 -50
0
50
100
150
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs GATE TO SOURCE VOLTAGE
1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 0 50 100 150 TJ, JUNCTION TEMPERATURE (oC) 200
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
NORMALIZED GATE THRESHOLD VOLTAGE
VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7
ID = 250A
0.6 -50
0 50 100 150 TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
1500
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
60 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25BVDSS GATE SOURCE VOLTAGE RL = 5.0 IG(REF) = 0.25mA VGS = 5V DRAIN SOURCE VOLTAGE 0 20 IG(REF) IG(ACT) t, TIME (s) 80 IG(REF) IG(ACT) 0 5 VGS, GATE TO SOURCE VOLTAGE (V)
1250 C, CAPACITANCE (pF) 1000 750 CISS 500 250 0 0 5 10 15 COSS CRSS
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
45
30
15
20
25
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
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RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) RL VDS VGS VGS
+
tOFF td(OFF) tr tf 90%
VDS
90%
0V RGS DUT
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Ig(REF) 0 VGS = 5V
DUT Ig(REF)
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORMS
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RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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